/**
  ******************************************************************************
  * @file    crg.h
  * @author  hyseim software Team
  * @date    01-Sep-2023
  * @brief   This file provides all the headers of the crg functions.
  ******************************************************************************
  * @attention
  *
  * Copyright (c) 2020 Hyseim. Co., Ltd.
  * All rights reserved.
  *
  * This software is licensed under terms that can be found in the LICENSE file
  * in the root directory of this software component.
  * If no LICENSE file comes with this software, it is provided AS-IS.
  *
  ******************************************************************************
  */

/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __CRG_H__
#define __CRG_H__

#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "chip_define.h"
#include "typedefine.h"
/* Exported types ------------------------------------------------------------*/
typedef enum {
    PLL_CLK     = 0,
    REF_CLK     = 1,
    OTG480_CLK  = 2
}CRG_SysClk_t;

 typedef enum {
    FUNC_DISABLE    = 0,
    FUNC_ENABLE     = 1
}CRG_FuncEnable_t;

 typedef struct {
    uint32_t pllClk;
    uint32_t cpuClk;
    uint32_t busClk;
    uint32_t perClk;
}CRG_Clk_t;

enum{
    CLK_DIV1  = 0,
    CLK_DIV2  = 1,
    CLK_DIV3  = 2,
    CLK_DIV4  = 3,
    CLK_DIV5  = 4,
    CLK_DIV6  = 5,
    CLK_DIV7  = 6,
    CLK_DIV8  = 7
};

typedef struct {
    uint32_t pllPreDiv;  /*  Control settings of PLL reference clock divider ratio:0~3 */
    uint32_t pllFbkInt;  /*  Control signal of PLL feedback divider ratio of the integer part:0~(2^8-1) */
    uint32_t pllFbkFra;  /*  Control signal of PLL feedback divider ratio of the fractional part :0~(2^24-1) */
    uint32_t pllPostDiv; /*  Control settings of VCO output clock divider ratio :0~3 */
}CRG_PllInit_t;

typedef struct {
    __IO uint32_t CFG_CRG_REG000;
    __IO uint32_t CFG_CRG_REG004;
    __IO uint32_t CFG_CRG_REG008;
    __IO uint32_t CFG_CRG_REG00C;
    __IO uint32_t CFG_CRG_REG010;
    __IO uint32_t CFG_CRG_REG014;
    __IO uint32_t CFG_CRG_REG018;
    __IO uint32_t CFG_CRG_REG01C;
    __IO uint32_t CFG_CRG_REG020;
    __IO uint32_t CFG_CRG_REG024;
    __IO uint32_t CFG_CRG_REG028;
    __IO uint32_t CFG_CRG_REG02C;
    __IO uint32_t CFG_CRG_REG030;
    __IO uint32_t CFG_CRG_REG034;
    __IO uint32_t CFG_CRG_REG038;
    __IO uint32_t CFG_CRG_REG03C;
    __IO uint32_t CFG_CRG_REG040;
    __IO uint32_t CFG_CRG_REG044;
    __IO uint32_t CFG_CRG_REG048;
    __IO uint32_t CFG_CRG_REG04C;
    __IO uint32_t CFG_CRG_REG050;
    __IO uint32_t CFG_CRG_REG054;
    __IO uint32_t CFG_CRG_REG058;
    __IO uint32_t CFG_CRG_REG05C;
    __IO uint32_t CFG_CRG_REG060;
    __IO uint32_t CFG_CRG_REG064;
    __IO uint32_t CFG_CRG_REG068;
    __IO uint32_t CFG_CRG_REG06C;
    __IO uint32_t CFG_CRG_REG100;
    __IO uint32_t CFG_CRG_REG104;
    __IO uint32_t CFG_CRG_REG108;
    __IO uint32_t CFG_CRG_REG10C;
    __IO uint32_t CFG_CRG_REG110;
    __IO uint32_t CFG_CRG_REG114;
    __IO uint32_t CFG_CRG_REG118;
    __IO uint32_t CFG_CRG_REG11C;
    __IO uint32_t CFG_CRG_REG120;
    __IO uint32_t CFG_CRG_REG124;
} CRG_t;
/* Exported constants --------------------------------------------------------*/

/* Exported macro ------------------------------------------------------------*/
#define CRG     ((CRG_t *)(CRG_BASE))
/* Exported functions ------------------------------------------------------- */
extern CRG_Clk_t sysClk;
extern void set_sysclk_500m_busclk_166m(void);
extern void set_sysclk_400m_busclk_200m(void);
extern void set_sysclk_300m_busclk_150m(void);
extern void set_sysclk_200m_busclk_100m(void);
extern void set_sysclk_150m_busclk_150m(void);
extern void set_sysclk_100m_busclk_50m(void);
extern void CRG_ClkTest(uint32_t clkPll, uint32_t cpuDiv, uint32_t busDiv, uint32_t perDiv);
extern void CRG_SetCpuBusPerClk(uint32_t clkPll, uint32_t cpuDiv, uint32_t busDiv, uint32_t perDiv);
#ifdef __cplusplus
}
#endif
#endif
/*******************(C)COPYRIGHT 2020 Hyseim ***********END OF FILE************/
